Summary
Conventional analog Phase-Locked Loop (PLL) occupies large area and is difficult to be reconfigured due to a bulky loop filter. In 2005, phase-domain all-digital phase-locked-loop (ADPLL) was proposed. It measured output phase of digitally controlled oscillator (DCO) using a time-to-digital converter (TDC). Unfortunately, designing fine-resolution TDC and wide dynamic range is power-consuming. In this project, instead of utilizing single sampling point per reference clock, we propose to oversample and digitize oscillator oscillator waveform which will produce enough digital samples to reconstruct, now in digital domain, the waveform and compare against a model waveform which will give precise frequency/phase and amplitude information. Thus, it is called, wave-locked loop (WLL) that will result in low-in-band phase noise, fast lock time, and wide-loop bandwidth that is no longer limited by reference clock. Preliminary data shows finer than 1-degree phase resolution even with 10% delay error in sampling clocks, and distortion from input waveform. This shows possibility to break the tradeoff in traditional TDC and improve robustness over PVT variations. Moreover, the design of building blocks which includes low-flicker-noise mm-wave LC Digitally-Controlled Oscillator (DCO) and small-sized ring oscillator with phase noise filtering will be investigated. Thus, this fellowship program studies an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system. The proposed synthesizer will be tapeout using advanced CMOS technology and will be measured to verify their performance.
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More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/746142 |
| Start date: | 01-04-2017 |
| End date: | 31-03-2019 |
| Total budget - Public funding: | 175 866,00 Euro - 175 866,00 Euro |
Cordis data
Original description
Conventional analog Phase-Locked Loop (PLL) occupies large area and is difficult to be reconfigured due to a bulky loop filter. In 2005, phase-domain all-digital phase-locked-loop (ADPLL) was proposed. It measured output phase of digitally controlled oscillator (DCO) using a time-to-digital converter (TDC). Unfortunately, designing fine-resolution TDC and wide dynamic range is power-consuming. In this project, instead of utilizing single sampling point per reference clock, we propose to oversample and digitize oscillator oscillator waveform which will produce enough digital samples to reconstruct, now in digital domain, the waveform and compare against a model waveform which will give precise frequency/phase and amplitude information. Thus, it is called, wave-locked loop (WLL) that will result in low-in-band phase noise, fast lock time, and wide-loop bandwidth that is no longer limited by reference clock. Preliminary data shows finer than 1-degree phase resolution even with 10% delay error in sampling clocks, and distortion from input waveform. This shows possibility to break the tradeoff in traditional TDC and improve robustness over PVT variations. Moreover, the design of building blocks which includes low-flicker-noise mm-wave LC Digitally-Controlled Oscillator (DCO) and small-sized ring oscillator with phase noise filtering will be investigated. Thus, this fellowship program studies an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system. The proposed synthesizer will be tapeout using advanced CMOS technology and will be measured to verify their performance.Status
CLOSEDCall topic
MSCA-IF-2016Update Date
28-04-2024
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