Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors

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Authors: L. Réveil, C. Mukherjee, C. Maneux, M. Deng, F. Marc, A. Kumar, A. Lecestre, G. Larrieu, A. Poittevin, I. O'Connor, O. Baumgartner and D. Pirker

Journal title: VLSI-SOC

Journal publisher: VLSI-SOC

Published year: 2022