Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs

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Authors: Ignacio M. Delgado-Lozano; Erica Tena-Sánchez; Juan Núñez; Antonio J. Acosta

Journal title: IEEE Embedded Systems Letters

Journal number: Early Access

Journal publisher: Institute of Electrical and Electronics Engineers

Published year: 2021

DOI identifier: 10.1109/les.2021.3122395

ISSN: 1943-0663