Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design

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Authors: Y. Wang, C. Mukherjee. H. Rezgui, M. Deng, C. Maneux, S. Mannaa, I. O’Connor, J. Müller, S. Pelloquin, G. Larrieu

Journal title: European Solid-State Device Research Conference (ESSDERC)

Journal publisher: IEEE

Published year: 2023

DOI identifier: 10.1109/essderc59256.2023.10268560