3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs

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Authors: R. Bishnoi, S. Diware, A. Gebregiorgis, S. Thomann, S. Mannaa, B. Deveautour, C. Marchand, A. Bosio, D. Deleruyelle, I. O'Connor, H. Amrouch, S. Hamdioui

Journal title: J. Exploratory Solid-State Computational Devices and Circuits

Journal publisher: IEEE

Published year: 2023

DOI identifier: 10.1109/jxcdc.2023.3309502

ISSN: 2329-9231